Which specs would you choose?

rdan · Sep 16, 2019

Planning to host mainly XenForo and some PHP Scripts.

Specs #1:

Intel Xeon E3 1240 V6

4 x 3.70 GHz

64GB DDR4

1TB SSD

$99/mo

Specs #2:

Intel Core i9 9900K

8 x 3.60 GHz

64GB DDR4

1TB NVMe SSD

$149/mo

Price isn't big deal.
Only downside for the i9, it is a Desktop CPU but having an advantage of NVMe.

rdan · Sep 16, 2019

This is from Reliablesite LA by the way, as it's hard looking for Singapore Dedicated Server except OVH.

rdan · Sep 16, 2019

PassMark - CPU Comparison Intel Xeon E3-1240 v6 vs Intel i9-9900K

eva2000 · Sep 16, 2019

i9 9900K won't have ECC memory like Intel Xeons would ECC memory - Wikipedia

Error-correcting code memory (ECC memory) is a type of computer data storage that can detect and correct the most-common kinds of internal data corruption. ECC memory is used in most computers where data corruption cannot be tolerated under any circumstances, such as for scientific or financial computing.

Typically, ECC memory maintains a memory system immune to single-bit errors: the data that is read from each word is always the same as the data that had been written to it, even if one of the bits actually stored has been flipped to the wrong state.[2] Most non-ECC memory cannot detect errors, although some non-ECC memory with parity support allows detection but not correction.
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The consequence of a memory error is system-dependent. In systems without ECC, an error can lead either to a crash or to corruption of data; in large-scale production sites, memory errors are one of the most-common hardware causes of machine crashes.[7] Memory errors can cause security vulnerabilities.[7] A memory error can have no consequences if it changes a bit which neither causes observable malfunctioning nor affects data used in calculations or saved. A 2010 simulation study showed that, for a web browser, only a small fraction of memory errors caused data corruption, although, as many memory errors are intermittent and correlated, the effects of memory errors were greater than would be expected for independent soft errors.[9]
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Many processors use error-correction codes in the on-chip cache, including the Intel Itanium and Xeon [28] processors, the AMD Athlon, Opteron, all Zen-[29] and Zen+-based[30] processors (EPYC, EPYC Embedded, Ryzen and Ryzen Threadripper), and the DEC Alpha 21264.[23][31]

As of 2006, EDC/ECC and ECC/ECC are the two most-common cache error-protection techniques used in commercial microprocessors. The EDC/ECC technique uses an error-detecting code (EDC) in the level 1 cache. If an error is detected, data is recovered from ECC-protected level 2 cache. The ECC/ECC technique uses an ECC-protected level 1 cache and an ECC-protected level 2 cache.[32] CPUs that use the EDC/ECC technique always write-through all STOREs to the level 2 cache, so that when an error is detected during a read from the level 1 data cache, a copy of that data can be recovered from the level 2 cache.
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Advantages and disadvantages[edit]
Ultimately, there is a trade-off between protection against unusual loss of data, and a higher cost.

ECC protects against undetected memory data corruption, and is used in computers where such corruption is unacceptable, for example in some scientific and financial computing applications, or in file servers. ECC also reduces the number of crashes that are especially unacceptable in multi-user server applications and maximum-availability systems.

Most motherboards and processors for less critical application are not designed to support ECC so their prices can be kept lower. Some ECC-enabled boards and processors are able to support unbuffered (unregistered) ECC, but will also work with non-ECC memory; system firmware enables ECC functionality if the ECC RAM is installed.

ECC memory usually involves a higher price when compared to non-ECC memory, due to additional hardware required for producing ECC memory modules, and due to lower production volumes of ECC memory and associated system hardware. Motherboards, chipsets and processors that support ECC may also be more expensive.

ECC may lower memory performance by around 2–3 percent on some systems, depending on the application and implementation, due to the additional time needed for ECC memory controllers to perform error checking.[35] However, modern systems integrate ECC testing into the CPU, generating no additional delay to memory accesses as long as no errors are detected.[22][36][37]
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if your data on server is important, you'd use ECC memory supported servers

eva2000 · Sep 16, 2019

more reading

ECC Memory vs. Non-ECC Memory - Why Get ECC Memory?

Is ECC Ram Required for a Hosting Dedicated Server? | Web Hosting Talk

Likelihood of a Memory Error
On any server with financial information or critical personal information, especially medical, any data loss or transcription error is unacceptable. Memory errors can cause security vulnerabilities, crashes, transcription errors, lost transactions, and corrupted or lost data.

The chances of a memory error occurring are estimated by experts to occur at rates of 2000–6000 per GB per year of uninterrupted operation. While desktop computers may not have noticeable memory errors very often, systems that operate for long periods of time, like data-centric servers, are at a greater risk. The risk also increases with larger amounts of memory and the age of the system. In a sensitive, high-demand work environment, all caution must be taken to prevent any likelihood of errors. The most common type of memory error is a single-bit error.

Single-Bit Errors
A single-bit error is when one bit (a binary 1 or 0) of a byte of data (8 bits) is changed to the opposite value (1 to 0, or vice versa). It is the most likely error to corrupt data, as it is so small that the computer may not automatically recognize it as incorrect data. Multiple bit errors (more than 1 bit being simultaneously affected), are more likely to occur, but less likely to be accepted by the computer as valid input. Multiple bit errors can be detected by single-bit ECC, but may not be corrected by it in all instances. Instead the system ignores it and reloads the data.

There are two types of single-bit memory errors: hard errors and soft errors. Physical factors, such as voltage stress, impact shock, temperature variation, or other nominal hardware damage, cause hard errors. This could be due to a manufacturer error, mishandled hardware, or it can simply be caused by stress over time. On the other hand, soft errors are caused by data being written or read differently than originally intended. As data is moved in and out of RAM, some corruption naturally occurs. Since bits retain their programmed value in the form of an electrical charge, there are many potential causes of these errors. Theories of why this occurs range from naturally occurring isotopes emitting Alpha particles, cosmic rays, magnetic variances, fluctuations in electricity flow, and even electromagnetic interference (EMI) from the computer itself.
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opposite argument from stackexchaneg/discourse guy talking about whether ECC is really needed at To ECC or Not To ECC as he was willing to risk it but he also did do extensive memory testing before deployment.

Yet another large scale study from 2012 discovered that RAM errors were dominated by permanent failure modes typical of hard errors:

Our study has several main findings. First, we find that approximately 70% of DRAM faults are recurring (e.g., permanent) faults, while only 30% are transient faults. Second, we find that large multi-bit faults, such as faults that affects an entire row, column, or bank, constitute over 40% of all DRAM faults. Third, we find that almost 5% of DRAM failures affect board-level circuitry such as data (DQ) or strobe (DQS) wires. Finally, we find that chipkill functionality reduced the system failure rate from DRAM faults by 36x
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.
In the end, we decided the non-ECC RAM risk was acceptable for every tier of service except our databases. Which is kind of a bummer since higher end Skylake Xeons got pushed back to the big Purley platform upgrade in 2017. Regardless, we burn in every server we build with a complete run of memtestx86 and overnight prime95/mprime, and you should too. There's one whirring away through endless memory tests right behind me as I write this.

I find it very, very suspicious that ECC – if it is so critical to preventing these random, memory corrupting bit flips – has not already been built into every type of RAM that we ship in the ubiquitous computing devices all around the world as a cost of doing business. But I am by no means opposed to paying a small insurance premium for server farms, either. You'll have to look at the data and decide for yourself. Mostly I wanted to collect all this information in one place so people who are also evaluating the cost/benefit of ECC RAM for themselves can read the studies and decide what they want to do.
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when i use to build my desktop computers (non-ECC memory), I'd be doing extensive memory testing which could run for days

rdan · Sep 16, 2019

Thanks, now I'm eyeing on this specs from hivelocity:

eva2000 · Sep 16, 2019

Intel Xeon E-2176G Coffee Lake cpus are just 1 generation behind the newer Intel Xeon E3-22xx Coffee Lake refrshes but still fast beasts. @gabel did Centmin Mod Nginx HTTP/2 benchmarks posted on this forum with such showed almost 2x faster than older Xeon E3-12xx v3-v6 series !.

Jay Chen · Sep 17, 2019

rdan said: ↑

Thanks, now I'm eyeing on this specs from hivelocity:
View attachment 6918
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I look forward for the day where I will need such a powerful machine

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